Slew-rate Enhancement Circuit Research Articles

An Output-Capacitorless Low-Dropout Regulator with Slew-Rate Enhancement.

A novel output-capacitorless low-dropout regulator (OCL-LDO) with an embedded slew-rate-enhancement (SRE) circuit is presented in this paper. The SRE circuit adopts a transient current-boost strategy to improve the slew rate at the gate of the power transistor when a large voltage spike at the output is detected. In addition, a feed-forward transconductance cell is introduced to form a push–pull output structure with the power transistor. The simulation results show that the maximum transient output voltage variation is when the load current is stepped from to in with a load capacitance of , and the settling time is . The proposed OCL-LDO consumes a quiescent current of and has a dropout voltage of for the maximum output current of .

A Transient-Enhanced Low-Dropout Regulator in 0.18-μm CMOS Technology

This paper presents a low-dropout voltage regulator (LDO) with a slew-rate enhancement circuit. The proposed slew-rate enhancement circuit was utilized to generate a large current for driving a large pass transistor and quicker charge and discharge of the parasitic capacitance. Hence, the transient response of the LDO was significantly enhanced owing to the improvement in the slew rate at the gate of the pass transistor. The proposed LDO regulator was designed and fabricated using the SMIC 0.18-[Formula: see text]m standard CMOS process, and its core area occupation was only 0.012[Formula: see text]mm2. The measurement results show that the output overshoot/undershoot voltages and settling times of the proposed LDO with SRE are 190[Formula: see text]mV/267[Formula: see text]ns and 174[Formula: see text]mV/233[Formula: see text]ns when the load current changes between 100[Formula: see text][Formula: see text]A and 100[Formula: see text]mA. It has a moderate figure-of-merit (FOM) of 0.267[Formula: see text]ns.

An ultra high slew rate recycling folded cascode OTA with 100-dB DC gain

This article presents an operational transconductance amplifier (OTA) with enhanced transconductance and slew rate. High transconductance is achieved by implementing local common-mode feedback (LCMF) in a new path. This new path also is used in providing the current splitting technique. The slew rate is significantly boosted due to a new slew rate enhancement circuit, a new quasi-floating gate (QFG) circuit and two non-linear current mirrors. The advantage of the proposed OTA is that its large-signal and small-signal figures of merits are remarkably improved compared to previous works. The post-layout simulation of the OTA is in TSMC 180 nm CMOS process. Monte Carlo and corner analyses shows the robustness of the OTA with variations of process and mismatch.

A new slew rate enhancement technique for operational transconductance amplifiers

AbstractThis paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded‐cascode amplifier (FCA) results in 7× slew rate improvement and 66.6% settling time reduction, while the frequency response and small‐signal operation of the amplifier are not degraded. The proposed SRE circuit is designed and simulated in a 0.13‐μm Complementary Metal‐Oxide‐Semiconductor (CMOS) technology. Post‐layout simulation results show that the circuit has a slew rate of 1465 V/μs and 9.75‐ns settling time for a total 3‐pF load capacitance while the power consumption is 841 μW at 1.2‐V supply voltage; that indicates 7‐time SR improvement with lower power dissipation compared to the conventional FCA and an excellent FOML of 6.26 ([V/μs] × pF/μA). Moreover, simulation results of the circuit for worst corner and temperature cases as well as 10% supply variation verify the robustness of the circuit against PVT changes.

带摆率增强电路的快速负载瞬态响应LDO研究

带摆率增强电路的快速负载瞬态响应LDO研究

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%.

A Fully Integrated FVF-Based Low-Dropout Regulator With Wide Load Capacitance and Current Ranges

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ( $C_{F}$ ) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100  μ A to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved.

A 99.96% efficiency capacitor-free low-dropout regulator with cross-couple class-AB push–pull input stage for wireless internet of things chip

A high efficiency capacitor-free low-dropout regulator (LDO) with the cross-couple class-AB push–pull input stage is presented for wireless internet of things and wireless senor network chip. Utilizing the proposed input stage, both load/line regulation and power supply rejection ratio (PSRR) are improved. Meanwhile, the transient response including the undershoot voltage, the overshoot voltage and the recovery time is optimized with the sub-threshold slew-rate enhancement circuit and the multiple loop compensation strategy. Simulation results show that the LDO only consumes a quiescent current of 41.8 μA, resulting in the energy efficiency of 99.96% at a 100-mA maximum load current (IL) from 1.2 V supply voltage using 0.18-μm CMOS process. When IL is switching from 0 A to 100 mA in 0.3 μs, the undershoot voltage and the overshoot voltage are about 131.62 mV and 126.31 mV while the corresponding recovery time are 0.77 μs and 0.55 μs with CL = 100 pF, respectively. Furthermore, PSRR at 1-kHz is boosted to − 58.8 dB at full load. Besides, an excellent line and load regulation of 0.24 mV/V and 1.76 μV/mA are obtained, respectively.

Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier

This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of $10.2~\mu \text{A}$ . It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of $0.22~\mu \text{s}$ is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of $0.1~\mu \text{s}$ .

A fast transient response and high current efficiency output-capacitorless low dropout regulator for low-power SoC applications

This paper presents an output capacitor-less low-dropout regulator (LDO) with a fast transient response and high current efficiency. The proposed slew rate enhancement circuit is activated only when the output voltage is instantaneously changed due to the transient of the load current. This method cannot only instantaneously increase the bias current source current for rapid output voltage recovery in order to enhance the load regulation but also reduce power consumption. The proposed LDO was fabricated using the standard 0.18 μm CMOS process. Measurement results revealed that the proposed LDO can operate from 1.2 to 1.8 V at an output voltage of 1 V and can provide loading current ranging from 3 to 100 mA. The current efficiency of the LDO was determined to be 99.96% at the maximal load current of 100 mA.

A robust inverter‐based amplifier versus PVT for discrete‐time integrators

SummaryWith the reduction of the supply voltage in modern complementary metal‐oxide‐semiconductor technologies, and by their intrinsic class AB behavior, inverter‐based amplifiers are suitable to replace classical operational transconductance amplifiers in switched capacitor circuits like sigma‐delta modulators. This paper presents a new inverter‐based amplifier which increases the reliability versus process, voltage, and temperature variations. A new biasing stage is proposed, which controls the bias current without losing the class AB behavior thanks to the use of biasing transistors operated in linear region and a slew rate enhancement circuit. This makes this amplifier more robust than simple inverters regarding to process, voltage, and temperature variations, reducing the worst‐case bias current spread from +140% to +20%, while costing only 15% consumption increase and keeping inverter dynamic strengths.

Design of High Stability LDO Based on CMOS Technology

This paper presents a low dropout linear regulator (LDO) structure designed by 0.18um CMOS process; it includes the bandgap voltage reference with good temperature characteristic, the error amplifier of high gain and good PSRR, the power adjustment transistor and resistance feedback network which have reasonable sizes, and slew rate enhancement circuit. The circuit simulation and layout design are successfully completed. The experimental results of LDO show that the circuit gain is 99.47dB, the phase margin is 67.27°, and the PSRR is 90.65dB. The linear adjustment rate is 0.3%, the load adjustment rate is 2.7%; the quiescent current is 56.1uA, the temperature drift coefficient is 8.04ppm/°C, and the layout area is 0.04mm2. This design meets the requirements that are low dropout, high stability and small area.

Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor

A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot.

Improved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique

paper presents a capacitor-less low drop-out (LDO) regulator with current mode transconductance amplifier & slew-rate enhancement circuit. The proposed current mode transconductance amplifier as error amplifier improves the slew rate & slew- rate enhancement circuit further senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short duration. Hence, transient response of LDO has been further improved using these techniques. The proposed LDO regulator will be designed and simulated in 180nm CMOS technology.

An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique

A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7μs and the maximum undershoot and overshoot are as low as 55mV and 30mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37mV/V and 2μV/mA, respectively.

Embedded capacitor multiplier gain boosting compensation for large-capacitive-load three-stage amplifier with slew rate enhancement

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.

A CMOS voltage buffer with slew-rate enhancement

A high slew-rate CMOS voltage buffer has been presented in this article. The slew-rate enhancement is achieved by an embedded driver stage activated by internal nodes in the voltage buffer through capacitive coupling. The capacitive coupling provides one-shot auto-off feature for the driver stage. Therefore, the drive stage can be turned off automatically after activation. The auto-off feature of the proposed driver stage guarantees a reliable operation. The proposed voltage buffer is implemented in a commercial 0.35-μm CMOS technology. The active chip area is 345 μm × 246 μm. The single supply voltage is 3.3 V, and the quiescent current is about 7 μA. When the proposed buffer drives a capacitive load of 220 pF, the measured positive and negative slew rates are 0.714 and 1.548 V/μs, respectively. The improvement corresponds to about 22 times for the positive slew rate and 48 times for the negative slew rate when comparing with the voltage buffer without the proposed the slew-rate enhancement circuit.

A Capacitorless LDO Regulator With Fast Feedback Technique and Low-Quiescent Current Error Amplifier

This brief presents an ultralow quiescent class-AB error amplifier (ERR AMP) of low dropout (LDO) and a slew-rate (SR) enhancement circuit to minimize compensation capacitance and speed up transient response designed in the 0.11-μm 1-poly 6-metal CMOS process. In order to increase the current capability with a low standby quiescent current under large-signal operation, the proposed scheme has a class-AB-operation operational transconductance amplifier (OTA) that acts as an ERR AMP. As a result, the new OTA achieved a higher dc gain and faster settling time than conventional OTAs, demonstrating a dc gain improvement of 15.8 dB and a settling time six times faster than that of a conventional OTA. The proposed additional SR enhancement circuit improved the response based on voltage-spike detection when the voltage dramatically changed at the output node.

A low-power low-voltage slew-rate enhancement circuit for two-stage operational amplifiers

A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers. The enhancer utilizes the class-AB input stage to improve current efficiency, while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier. During the slewing period, the enhancer detects input differential voltage of the amplifier, and produces external enhancement currents for the amplifier, driving load capacitors to charge/discharge faster. Simulation results show that, for a large input step, the enhancer reduces settling time by nearly 50%. When the circuit is employed in a sample-and-hold circuit, it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB. The proposed circuit is very suitable to operate under a low voltage (1.2 V or below) with a standby current of 200 μA.

A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application

A low-dropout regulator for on-chip application with active feedback and a slew-rate enhancement circuit to minimize compensation capacitance and speed up transient response is presented in this brief. The idea has been modeled and experimentally verified in a standard 0.35-?m CMOS process. The total compensation capacitance is 7 pF. From experimental results, the implemented regulator can operate from a supply voltage of 1.8-4.5 V with a minimum dropout voltage of 0.2 V at a maximum 100-mA load and I Q of 20 ?A.